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<div class="title">GPIO_TypeDef结构体 参考<div class="ingroups"><a class="el" href="group___c_m_s_i_s.html">CMSIS</a> &raquo; <a class="el" href="group__wb32l003.html">Wb32l003</a> &raquo; <a class="el" href="group___device___peripheral__peripherals.html">Device_Peripheral_peripherals</a></div></div>  </div>
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成员变量</h2></td></tr>
<tr class="memitem:ae8a1a7d534832448e73695966f7827b6"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_g_p_i_o___type_def.html#ae8a1a7d534832448e73695966f7827b6">DIRCR</a></td></tr>
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<h2 class="groupheader">结构体成员变量说明</h2>
<a id="a5d3e66e9454bd8d038aaf07131d1ab19"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5d3e66e9454bd8d038aaf07131d1ab19">&#9670;&nbsp;</a></span>AFR</h2>

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          <td class="memname">__IOM uint32_t AFR</td>
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<p>GPIO multiplex function register, Address offset: 0x048 </p>

</div>
</div>
<a id="a6734ec4e5bba3e069477653906944135"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6734ec4e5bba3e069477653906944135">&#9670;&nbsp;</a></span>DBCLKCR</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">__IOM uint32_t DBCLKCR</td>
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<p>GPIO input debounce clock config register, Address offset: 0x038 </p>

</div>
</div>
<a id="ae8a1a7d534832448e73695966f7827b6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae8a1a7d534832448e73695966f7827b6">&#9670;&nbsp;</a></span>DIRCR</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">__IOM uint32_t DIRCR</td>
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<p>GPIO input output model register, Address offset: 0x000 </p>

</div>
</div>
<a id="a47f272c9ec8238f602ec0e80c536da52"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a47f272c9ec8238f602ec0e80c536da52">&#9670;&nbsp;</a></span>DRVCR</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">__IOM uint32_t DRVCR</td>
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<p>GPIO driver strength config register, Address offset: 0x044 </p>

</div>
</div>
<a id="aacbba227b370bf944ed4cc3e6efc69e0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aacbba227b370bf944ed4cc3e6efc69e0">&#9670;&nbsp;</a></span>IDR</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">__IOM uint32_t IDR</td>
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<p>GPIO input data register, Address offset: 0x00C </p>

</div>
</div>
<a id="a3b02af11118d7042fa1770f09861fab1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3b02af11118d7042fa1770f09861fab1">&#9670;&nbsp;</a></span>INDBEN</h2>

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<div class="memproto">
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        <tr>
          <td class="memname">__IOM uint32_t INDBEN</td>
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</div><div class="memdoc">
<p>GPIO input debounce and synchronous enable register, Address offset: 0x034 </p>

</div>
</div>
<a id="a31bc066e8efe6b1f92d027360f641a19"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a31bc066e8efe6b1f92d027360f641a19">&#9670;&nbsp;</a></span>INTANY</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t INTANY</td>
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</div><div class="memdoc">
<p>GPIO edge trigger interrupt register, Address offset: 0x028 </p>

</div>
</div>
<a id="a6257a1dba4f7f3f833c7fe9c66a5713f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6257a1dba4f7f3f833c7fe9c66a5713f">&#9670;&nbsp;</a></span>INTCLR</h2>

<div class="memitem">
<div class="memproto">
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          <td class="memname">__IOM uint32_t INTCLR</td>
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<p>GPIO interrupt clear register, Address offset: 0x01C </p>

</div>
</div>
<a id="ae882b3f7e12b9f3b74cf834193554d32"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae882b3f7e12b9f3b74cf834193554d32">&#9670;&nbsp;</a></span>INTEN</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">__IOM uint32_t INTEN</td>
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<p>GPIO inerrupt enable register, Address offset: 0x010 </p>

</div>
</div>
<a id="a18d7c532ce57256c65b0f32459aa7295"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a18d7c532ce57256c65b0f32459aa7295">&#9670;&nbsp;</a></span>INTPOLCR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t INTPOLCR</td>
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</div><div class="memdoc">
<p>GPIO interrupt sytle value register, Address offset: 0x024 </p>

</div>
</div>
<a id="a9a770295af8e63a46404a9ee06a7d001"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9a770295af8e63a46404a9ee06a7d001">&#9670;&nbsp;</a></span>INTTYPCR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t INTTYPCR</td>
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</div><div class="memdoc">
<p>GPIO interrupt style register, Address offset: 0x020 </p>

</div>
</div>
<a id="a19f836e193cbbc2e9e5243156de79ff3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a19f836e193cbbc2e9e5243156de79ff3">&#9670;&nbsp;</a></span>MSKINTSR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t MSKINTSR</td>
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</div><div class="memdoc">
<p>GPIO interrupt status register, Address offset: 0x018 </p>

</div>
</div>
<a id="aae16fbb816f68f7682fdae13fa86a34c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aae16fbb816f68f7682fdae13fa86a34c">&#9670;&nbsp;</a></span>ODCLR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t ODCLR</td>
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</div><div class="memdoc">
<p>GPIO output clear register, Address offset: 0x030 </p>

</div>
</div>
<a id="ab60e87b8f95ece1e0dcc1b1455beb518"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab60e87b8f95ece1e0dcc1b1455beb518">&#9670;&nbsp;</a></span>ODR</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t ODR</td>
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</div><div class="memdoc">
<p>GPIO output data register, Address offset: 0x008 </p>

</div>
</div>
<a id="a686b1a465d965de93c21fd5661d661cc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a686b1a465d965de93c21fd5661d661cc">&#9670;&nbsp;</a></span>ODSET</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t ODSET</td>
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<p>GPIO output setting register, Address offset: 0x02C </p>

</div>
</div>
<a id="a3814a31c008490687cd68e980c58609e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3814a31c008490687cd68e980c58609e">&#9670;&nbsp;</a></span>OTYPER</h2>

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<div class="memproto">
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        <tr>
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<p>GPIO output type register, Address offset: 0x004 </p>

</div>
</div>
<a id="a298d23901c9eae457ea0d4c711090c9c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a298d23901c9eae457ea0d4c711090c9c">&#9670;&nbsp;</a></span>PUPDR</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">__IOM uint32_t PUPDR</td>
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</div><div class="memdoc">
<p>GPIO pullup and pulldown register, Address offset: 0x03C </p>

</div>
</div>
<a id="ad33b337b62c7f413fbbfb8857641572a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad33b337b62c7f413fbbfb8857641572a">&#9670;&nbsp;</a></span>RAWINTST</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">__IOM uint32_t RAWINTST</td>
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<p>GPIO interrupt raw status register, Address offset: 0x014 </p>

</div>
</div>
<a id="af7b4808ee39e82a1d34c73ecf849fe49"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af7b4808ee39e82a1d34c73ecf849fe49">&#9670;&nbsp;</a></span>SLEWCR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__IOM uint32_t SLEWCR</td>
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</div><div class="memdoc">
<p>GPIO voltage convertion speed control register, Address offset: 0x040 </p>

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